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Bug #55389

closed

[pwl] endianness issue with WriteLogCacheEntry encoding

Added by Ilya Dryomov about 2 years ago. Updated almost 2 years ago.

Status:
Resolved
Priority:
Normal
Assignee:
Target version:
-
% Done:

0%

Source:
Tags:
Backport:
pacific,quincy
Regression:
No
Severity:
3 - minor
Reviewed:
Affected Versions:
ceph-qa-suite:
Pull request ID:
Crash signature (v1):
Crash signature (v2):

Description

  union {
    uint8_t flags;
    uint8_t flags = 0;
    struct {
      uint8_t entry_valid :1; /* if 0, this entry is free */
      uint8_t sync_point :1;  /* No data. No write sequence number. Marks sync
                                 point for this sync gen number */
      uint8_t sequenced :1;   /* write sequence number is valid */
      uint8_t has_data :1;    /* write_data field is valid (else ignore) */
      uint8_t discard :1;     /* has_data will be 0 if this is a discard */
      uint8_t writesame :1;   /* ws_datalen indicates length of data at write_bytes */
    };
  };
  DENC(WriteLogCacheEntry, v, p) {
    DENC_START(1, 1, p);
    ... 
    denc(v.flags, p);
    ...
    DENC_FINISH(p);
  }

Bit fields are not suit for anything where layout actually matters. Here, depending on the platform and the compiler, entry_valid can refer to either least significant bit of flags or the most significant bit:

An implementation may allocate any addressable storage unit large enough to hold a bit-field. If enough space remains, a bit-field that immediately follows another bit-field in a structure shall be packed into adjacent bits of the same unit. If insufficient space remains, whether a bit-field that does not fit is put into the next unit or overlaps adjacent units is implementation-defined. The order of allocation of bit-fields within a unit (high-order to low-order or low-order to high-order) is implementation-defined. The alignment of the addressable storage unit is unspecified.


Related issues 2 (0 open2 closed)

Copied to rbd - Backport #55472: pacific: [pwl] endianness issue with WriteLogCacheEntry encoding ResolvedIlya DryomovActions
Copied to rbd - Backport #55473: quincy: [pwl] endianness issue with WriteLogCacheEntry encoding ResolvedIlya DryomovActions
Actions #1

Updated by Ilya Dryomov about 2 years ago

  • Description updated (diff)
Actions #2

Updated by jianpeng ma about 2 years ago

which platform can reproduce this ?

Actions #3

Updated by Ilya Dryomov about 2 years ago

Anything big-endian, such as IBM Power in big-endian mode, IBM Z, etc.

Actions #4

Updated by Ilya Dryomov about 2 years ago

  • Status changed from New to Fix Under Review
  • Assignee set to CONGMIN YIN
  • Pull request ID set to 46025
Actions #5

Updated by Ilya Dryomov about 2 years ago

  • Backport set to pacific,quincy
Actions #6

Updated by Ilya Dryomov almost 2 years ago

  • Status changed from Fix Under Review to Pending Backport
Actions #7

Updated by Backport Bot almost 2 years ago

  • Copied to Backport #55472: pacific: [pwl] endianness issue with WriteLogCacheEntry encoding added
Actions #8

Updated by Backport Bot almost 2 years ago

  • Copied to Backport #55473: quincy: [pwl] endianness issue with WriteLogCacheEntry encoding added
Actions #9

Updated by Ilya Dryomov almost 2 years ago

  • Status changed from Pending Backport to Resolved
Actions

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